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发表于 2012-11-30 00:35 · 台湾
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看来很老旧啊,这颗CPU。
The PowerPC 740 and 750 (codename Arthur)[2] were introduced in late 1997 as an evolutionary replacement for the PowerPC 603e. Enhancements included a faster 60x system bus (66 MHz), larger L1 caches (32 KB instruction and 32 KB data), a second integer unit, an enhanced floating point unit, and higher core frequency. The 750 had support for an optional 256, 512 or 1024 KB external unified L2 cache. The cache controller and cache tags are on-die. The cache was accessed via a dedicated 64-bit bus.
The 740 and 750 added dynamic branch prediction and a 64-entry branch target instruction cache (BTIC). Dynamic branch prediction uses the recorded outcome of a branch stored in a 512-entry by 2-bit branch history table (BHT) to predict its outcome. The BTIC caches the first two instructions at a branch target.
The 740/750 models had 6.35 million transistors and was initially manufactured by IBM and Motorola in an aluminium based fabrication process. The die measured 67 mm2 at 0.26 μm and it reached speeds of up to 366 MHz while consuming 7.3 W.
In 1999, IBM fabricated versions in a 0.20 μm process with copper interconnects, which increased the frequency up to 500 MHz and decreased power consumption to 6 W and the die size to 40 mm2.
The 740 slightly outperformed the Pentium II while consuming far less power and with a smaller die. The off-die L2 cache of the 750 increased performance by approximately 30% in most situations. The design was so successful that it quickly surpassed the PowerPC 604e in integer performance, causing a planned 604 successor to be scrapped.
The PowerPC 740 is completely pin compatible with the older 603, allowing upgrades to the PowerBook 1400, 2400, and even a prototype PowerBook 500/G3. The 750 with its L2 cache bus required more pins and thus a different package, a 360-pin ball grid array (BGA).
The PowerPC 750 was used in many computers from Apple, including the original iMac. |
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