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发表于 2013-1-14 17:51 · 河北
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本帖最后由 03163135651 于 2013-1-15 12:22 编辑
MMC1,MAPPER1的改造方法。
MMC1在当时来说,是非常厉害的芯片,
CHR可以随意切换,功能非多。
所以改烧录卡也相对于简单很多。
但是PCB板子也分很多种:SKROM、SLROM、SNROM、SJROM等,
改卡的方法基本一样。
由于使用了MMC1的卡带,时序比较特殊,所以对CHR的FLASH芯片要求比较高。
这里只推荐AMD的芯片,其他芯片目前没有成功的案例。
大家也不用尝试其他芯片。
MMC1的资料,方便大家查询
MMC1 pinoutFrom Nesdev wiki
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MMC1 Chip: (24 pin shrink-DIP)
Comes in several varieties: 'MMC1', 'MMC1A', and 'MMC1B2'
.-- \/ --.
PRG A14 (r) <- |01 24| - +5V
PRG A15 (r) <- |02 23| <- M2 (n)
PRG A16 (r) <- |03 22| <- CPU A13 (s)
PRG A17 (r) <- |04 21| <- CPU A14 (n)
PRG /CE (r) <- |05 20| <- /ROMSEL (n)
WRAM CE (w) <- |06 19| <- CPU D7 (s)
CHR A12 (r) <- |07 18| <- CPU D0 (s)
CHR A13 (r) <- |08 17| <- CPU R/W
CHR A14 (r) <- |09 16| -> CIRAM A10 (n)
CHR A15 (r) <- |10 15| <- PPU A12 (n)
CHR A16 (r) <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`--- ---'
(r) - this pin connects to the ROM chips only
(n) - this pin connects to the NES connector only
(s) - this pin is shared with the NES connector and ROM chips
(w) - this pin connects to the WRAM only
As with many other ASIC mappers, parts of the pinout are often repurposed:
SEROM, SHROM, SH1ROM: only supports 32kiB at a time banking
.--\/--.
n/c <- |01 24| - +5V
PRG A15 (r) <- |02 23| <- M2 (n)
CPU A14 (n) -> PRG A14 (r)
SNROM: loses CHR banking for a PRG-RAM disable
n/c <- |08 17| <- CPU R/W
n/c <- |09 16| -> CIRAM A10 (n)
n/c <- |10 15| <- PPU A12 (n)
WRAM /CE (w) <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`------'
SOROM: loses CHR banking for PRG-RAM banking
n/c <- |08 17| <- CPU R/W
n/c <- |09 16| -> CIRAM A10 (n)
WRAM A14 (w) <- |10 15| <- PPU A12 (n)
n/c <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`------'
SOROM is actually implemented using the WRAMs' /CE inputs and an inverter to select only one RAM at a time.
SUROM: loses CHR banking for PRG-ROM banking
n/c <- |08 17| <- CPU R/W
n/c <- |09 16| -> CIRAM A10 (n)
n/c <- |10 15| <- PPU A12 (n)
PRG A18 (r) <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`------'
SXROM: loses CHR banking for PRG-ROM and PRG-RAM banking
n/c <- |08 17| <- CPU R/W
WRAM A14 (w) <- |09 16| -> CIRAM A10 (n)
WRAM A15 (w) <- |10 15| <- PPU A12 (n)
PRG A18 (r) <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`------'
Since the PPU A12 input's only purpose is to switch the CHR A12 .. A16 outputs, it's not clear why Nintendo didn't tie the MMC1's PPU A12 input low and connect CHR RAM A12 directly to the cartridge edge.
改造方法:
PRG接线方式:
1 脚:A18 +5V
2 脚:A16 接 原芯片 24pin, MMC PRG A16
31脚:/WE 接 金手指 14pin, 14PIN CPU R/W
30脚:A17 接 原芯片 1pin
24脚:/OE 接 原芯片 22pin, MMC PRG /OE
22脚:/CE 接 金手指 44pin, CPU /ROMCS
CHR接线方式:
1 脚:A18 留空 (不动)
2 脚:A16 接 原芯片 24pin, MMC CHR A16
31脚:/WE 接 金手指 47pin 47PIN PPU /WR
30脚:A17 接 +5V (不动)
24脚:/OE 接 原芯片 2pin, MMC CHR /OE
22脚:/CE 接 原芯片 31pin, 56PIN PPU A13
.--\/--.
PRG A14 (r) <- |01 24| - +5V
PRG A15 (r) <- |02 23| <- M2 (n)
PRG A16 (r) <- |03 22| <- CPU A13 (s)
PRG A17 (r) <- |04 21| <- CPU A14 (n)
PRG /CE (r) <- |05 20| <- /ROMSEL (n)
WRAM CE (w) <- |06 19| <- CPU D7 (s)
CHR A12 (r) <- |07 18| <- CPU D0 (s)
n/c <- |08 17| <- CPU R/W
n/c <- |09 16| -> CIRAM A10 (n)
n/c <- |10 15| <- PPU A12 (n)
WRAM /CE (w) <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`------'
采用6264芯片,单芯片512K的连接方式
WRAM连接MMC1第8PIN
PRG A18连接 MMC1第11PIN
512K接线
WRAM /CE (w) <- |08 17| <- CPU R/W
n/c <- |09 16| -> CIRAM A10 (n)
n/c <- |10 15| <- PPU A12 (n)
PRG A18 (r) <- |11 14| <- PPU A11 (s)
GND - |12 13| <- PPU A10 (s)
`------'
到此MMC1改卡方法介绍完毕,不懂的就回帖提出吧。
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